1. Field of the Invention
One embodiment of the present invention relates to a semiconductor memory device including a semiconductor or another semiconductor device, a driving method thereof, a manufacturing method thereof, and the like.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the specification, the drawings, and the claims (hereinafter referred to as “this specification and the like”) relates to an object, a method, or a manufacturing method. Furthermore, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a method of driving any of them, and a method of manufacturing any of them.
2. Description of the Related Art
In a general dynamic random access memory (DRAM), a memory cell includes one transistor (1T) and one capacitor (1C). Such a 1T1C DRAM is a memory capable of retaining data by accumulating electric charge in a capacitor and thus has no limit on the number of times of writing in principle. As a high-capacity memory device, the DRAM is incorporated in a number of electronic devices because of writing and reading at relatively high speed and a small number of memory cells, which easily enable high integration. The 1T1C DRAM performs data reading in such a manner that electric charge accumulated in the capacitor is released to a bit line and a change in a potential is measured; therefore, the electrostatic capacitance of the capacitor needs to be kept at a certain value or more. As a result, miniaturization of its memory cell makes it more and more difficult to keep necessary electrostatic capacitance.
Besides the 1TC1C memory cell, a memory cell called a gain cell including two or three transistors has been proposed (e.g., Patent Document 1 and 2). In the gain cell, the amount of electric charge can be amplified by a read transistor and the electric charge can be supplied to a bit line; therefore, it is possible to reduce the capacitance of the capacitor.
It has been also proposed to use a transistor including an oxide semiconductor layer having a region where a channel is formed (hereinafter referred to as an “OS transistor”) as a write transistor in a gain cell (e.g., Patent Document 3). In Patent Document 3, even when power is not supplied, stored data can be retained by utilizing a characteristic of extremely small off-state current of the OS transistor.